The present invention relates to a clock frequency synchronizer on a decoder side and, more particularly, to a clock frequency synchronizer for receiving a count value of system clock on an encoder side which is transferred from the encoder as a reference count value, and generating system clock on the decoder side which is synchronous in frequency with the system clock on the encoder side on the basis of the reference count value.
There is a data multiplexing transmission system called a transport stream (MPEG2-TS) in the ISO/IEC MPEG2 system. In a picture transmitting system for multiplexing and transmitting picture, sound, data, etc through a network by using such a transport stream (MPEG2-TS), it is necessary for the decoder side to reproduce the system clock which is synchronous in frequency with the system clock (27 MHz) for encoding a picture used on the encoder side.
For this purpose, in the MPEG2-TS, the encoder inserts a PCR (Program Clock Reference) value into each transport packet TPP composed of 188 bytes before transmission, and the decoder extracts the PCR value and generates a system clock on the decoder side which is synchronous in frequency with the system clock on the encoder side on the basis of the PCR value, as shown in FIG. 14. The PCR value is a count value obtained by counting the system clocks on the encoder side in a packet transmission period, and it is represented by 42 bits. The transport packet TPP is composed of an information field portion IFL into which various control information is inserted and a payload PLD for transmitting data. A PCR value of 42 bits is inserted into a predetermined place of the information field portion IFL.
The decoder is provided with a system clock generator for generating a system clock, an internal counter for counting the system clocks, and an arithmetic processor. The arithmetic processor obtains the number .DELTA.B of system clocks counted by the internal counter during the period between the arrival of the precedent PCR value and the arrival of the current PCR value, and the difference .DELTA.A between the precedent PCR value and the current PCR value. The difference .DELTA.A between the precedent PCR value and the current PCR value is an increment in the number of system clocks on the encoder side. Therefore, the value obtained by dividing the difference between .DELTA.A and .DELTA.B by the PCR arrival interval .DELTA.T is a frequency deviation of the system clock on the decoder side from the frequency of the system clock on the encoder side. The arithmetic processor obtains the frequency deviation by dividing the difference between .DELTA.B and .DELTA.A by .DELTA.T, and controls the oscillation frequency of the system clock generator on the decoder side so that the frequency deviation becomes zero. In this manner, the synchronism of the frequencies of the system clocks on the encoder side and the decoder side is established.
FIG. 15 shows the structure of a clock frequency synchronizing circuit in a conventional decoder. In FIG. 15, the reference numeral 1 represents a reference PCR storage portion for storing the PCR value of 42 bits which is transmitted from the encoder of an MPEG2 system separator (not shown). The reference PCR storage portion 1 is composed of a Base portion of 33 bits and an extension portion of 9 bits, i.e, 42 bits in total. The reference numeral 2 represents an internal counter for counting the system clocks of the decoder. The internal counter 2 is composed of a Base portion of 33 bits and an extension portion of 9 bits, i.e, 42 bits in total. The Extension portion counts from 0 to 299 and the Base portion counts up the carry pulses supplied from the Extension portion. An internal counter 2 is capable of counting the system clocks of 27 MHz for a little over 24 hours. The reference numeral 3 represents an operation controller, which receives a PCR arrival end signal from the MPEG2 system separator and generates a latch signal Latch and an interruption signal IRQ, as shown in FIG. 14. That is, the operation controller 3 (1) executes control for generating a latch signal Latch when the arrival of a PCR value from the encoder has ended so as to latch the reference PCR value to the reference PCR storage portion 1, and (2) control for generating an interruption signal IRQ when the arrival of a PCR value has ended.
The reference numeral 4 represents a register from which a CPU reads the reference PCR value, 5 a register from which the CPU reads the count value B of the internal counter 2, and 6 a frequency setting value register of N bits for a voltage controlled clock oscillator. If it is assumed that the frequency drawing range is .+-.100 ppm and the frequency correction value of the minimum bit is 1 ppm/LSB, for example, N=8. The reference numeral 7 denotes a DA converter for converting the data of N bits set in the register into a DC voltage, 8 an amplifier for controlling the gain between the dynamic range of the voltage output from the DA converter 7 and the input variable voltage of a voltage controlled clock oscillator at the next stage, and 9 the voltage controlled clock oscillator (VCXO) for generating a system clock of a nominal frequency 27 MHz. It is necessary that the voltage controlled clock oscillator 9 has a variable frequency range not less than the frequency drawing range. The commercially available voltage controlled clock oscillator 9 generally stipulates the minimum variable frequency per unit voltage, and has the following specification, for example.
(1) Variable frequency per unit voltage: more than .+-.100 ppm/V (actually about .+-.150 ppm/V), and
(2) input variable voltage range: +2.5 V.+-.2 V. Since the input variable voltage is .+-.2 V and the variable frequency is .+-.100 ppm/V, the clock oscillator 9 can vary the frequency in the range of a little over .+-.200 ppm.
The reference numeral 10 denotes a central processing unit (CPU), which is composed of hardwares such as an arithmetic processor (not shown), a program memory (ROM), a data memory (RAM), and an input/output interface. The CPU 10 executes clock synchronization control by program control. The reference numeral 10a represents a CPU clock generator, and 10b a CPU bus.
An MPEG2 system separator (not shown) inputs a PCR value of 42 bits contained in each transport packet TPP of the received MPEG2 transport stream to the reference PCR storage portion 1 in serial bits, monitors the end of the arrival of the PCR values, and inputs a PCR arrival end signal to the operation controller 3 when it receives the last PCR bit.
The operation controller 3 then generates a latch signal, stores the PCR value in the reference PCR storage portion, and outputs the PCR value A. As a result, the PCR value A is stored in the register 4. And the latest count value B of the internal counter 2 is constantly stored in the register 5.
Thereafter, the operation controller 3 inputs the interruption signal IRQ to the CPU 10. The CPU 10 which has recognized interruption reads the PCR value which has lately arrived and the count value B of the internal counter 2 which is in progress of counting from the registers 4 and 5, respectively. Since both the precedent PCR value and the precedent count value are stored in the RAM built in the CPU 10, the CPU 10 obtains the difference .DELTA.A between the precedent and current PCR values and the difference .DELTA.B between the precedent and current count values (see FIG. 16). The CPU 10 also counts the CPU clock so as to obtain the time elapsed from the arrival of the precedent PCR value to the arrival of the current PCR value, thereby calculating the PCR arrival interval .DELTA.T.
The CPU 10 then obtains the frequency deviation .DELTA.F from the following formula: EQU .DELTA.F (ppm)=(.DELTA.B-.DELTA.A)/(.DELTA.T.times.27.times.10.sup.6).
In other words, the value .DELTA.F (ppm) is calculated by dividing the frequency deviation generated during 1 second by a nominal frequency 27 MHz (=27.times.10.sup.6 Hz).
When the frequency deviation .DELTA.F (ppm) is obtained, the CPU 10 sets the frequency deviation .DELTA.F in the register 6. The DA converter 7 converts the frequency data set in the register 6 into an analog voltage. If it is assumed that the register 6 has 8 bits, it is possible to set the frequency deviation in 255 stages. If it is assumed that the frequency changing unit is 1 ppm/LSB, the frequency change of about .+-.128 ppm is possible.
The amplifier 8 has the following gain characteristic with respect to the input value to the DA converter 7 when the variable frequency characteristic of the clock oscillator 9 is .+-.100 ppm/V:
(1) the output frequency of the clock oscillator 9 is 27.0 MHz at the central value 80 h (128 d),
(2) the output frequency of the clock oscillator 9 is 27.0 MHz+127 ppm at the maximum value FFh (255 d), and
(3) the output frequency of the clock oscillator 9 is 27.0 MHz+128 ppm at the minimum value OOh (000 d),
wherein h represents hexa and d decimal.
The voltage controlled clock oscillator 9 changes the frequency in the direction in which the frequency deviation decreases on the basis of the output of the amplifier 8. The above-described control is thereafter executed whenever a PCR value arrives.
The actual frequency of a system clock changes more largely than the frequency deviation .DELTA.F which is set in the register 6 by the CPU 10. For this reason, the frequency deviation of the system clock of the encoder and the decoder undergoes a transition (image) shown in FIG. 17, and the average frequency of the system clock of the decoder in a long time becomes synchronous with the frequency of the system clock of the encoder.
The above-described operational environment of the conventional MPEG2-TS will be summed up in the following.
(a) In the MPEG2-TS, the PCR supply interval of the encoder is only stipulated as not more than 100 ms, and the necessity of a regular interval is not demanded.
(b) The MPEG2-TS is generally used to transmit picture/voice/data, etc by using a network and the decoder is disposed at a remote place from the encoder. Therefore, a jitter generates in a signal transmission time or a transmission clock in the network, and it is necessary to widen the variable range of the system clock on the decoder side due to the jitter. For example, the frequency change of the system clock (27 MHz) in the encoder which is stipulated in the MPEG2-TS standard is within .+-.30 ppm, and the jitter of the line clock generated when a general digital private line is used for a network for picture transmission is about .+-.30 ppm. It is therefore necessary to respond to a frequency change of .+-.60 ppm in total, so that the necessary variable range of the frequency of the system clock on the decoder side is about 27 MHz.+-.100 ppm including a margin.
(c) The PCR arrival interval in the decoder is calculated by counting the CPU clock during the interval of the internal interruption IRQ which generates every time the PCR arrives.
(d) In the generally commercially available voltage controlled clock oscillator of which nominal frequency is 27 MHz which is used on the decoder side, the minimum value of the frequency change per unit controlled voltage is only stipulated, and the actual frequency change is different in clock oscillators.
In the conventional system, the PCR arrival interval is counted by the software timer (count of the CPU clock), as is clear from (c). An ordinary software timer called an interval timer counts the time by accumulating the interruptions which generate at an interval of several 10 ms to several 100 ms. Since the PCR arrival interval is not more than 100 ms, as is clear from (a), an interval timer for counting a unit of about 1 ms is necessary in order to accurately count the PCR arrival interval. However, when an interval timer for counting such a short time interval is used, the number of times of interruption, namely, the number of times of processing interruption increases, so that the load of the CPU disadvantageously increases.
In addition, when the PCR arrival interval is counted by the interval timer (software timer), the recognition of interruption by the CPU and the processing time of the CPU become unstable. For this reason, in the conventional system, a large error in time is disadvantageously contained in the result of the calculation of the PCR arrival interval.
Furthermore, in the conventional system, there is no processing system for absorbing the network jitter (the jitter in the PCR arrival interval generated in the network) explained in (b).
As explained in (d), in the frequency change per unit voltage in the voltage controlled clock oscillator, only the minimum value is stipulated. For this reason, in the conventional system, even if the frequency setting value is set in the register so as to obtain an expected frequency, there is a deviation between the expected frequency and the actual output frequency of the clock oscillator, so that the frequency synchronism is not obtained (see FIG. 17).